Referring to FIG. 8, a MESFET having the conventional gate structure having two recesses on different levels, i.e., a two-stage recess, is shown in cross section. This FET has a GaAs substrate 1 and an n-type GaAs active layer 2 formed on the substrate 1. A first recess 6 is formed in a given location in the active layer 2. A second recess 5 is formed in the center of the bottom surface of the first recess 6. Thus, a hole 20 is formed by the upper wider recess 5 and the lower narrower recess 6.
A gate electrode 4 is located in the center of the bottom surface of the second lower recess 5 and in Schottky contact with the active layer 2. The gate electrode 4 is formed by successively depositing a layer of titanium, a layer of platinum, and a layer of gold (none of which are shown) on the active layer 2. A source electrode 3a and a drain electrode 3b are formed on opposite sides of the hole 20 consisting of the two recesses, and are in ohmic contact with the active layer 2.
MESFETs of this doubly recessed gate structure have enjoyed wide acceptance as high-output transistors. They are characterized by small consumption of electric power and a high power efficiency. The power efficiency of a MESFET is the ratio of the electric power supplied from the power supply to the device to the output power from the device, and is given by EQU (P.sub.OUT -P.sub.IN)/(V.sub.DD .times.I.sub.DD)
where V.sub.DD is the potential applied to the device from the power supply, I.sub.DD is the current flowing between the source and the drain, P.sub.OUT is the output power, and P.sub.IN is the input power, as shown in FIG. 11.
The doubly recessed gate structure produces a smaller source-drain resistance and thus provides a higher power efficiency than FETs having a singly recessed gate structure and FETs having no recess. It is considered today that this advantage of the doubly recessed structure arises from the fact that the resistive component between the source and the drain is smaller than that of the singly recessed structure.
This MESFET is fabricated in the manner described now. First, as shown in FIG. 9(a), the n-type active layer 2 consisting of the same material as the GaAs substrate 1 is formed on the substrate 1 by ion implantation or epitaxy. The GaAs substrate may be replaced by a substrate of Si or InP. In this case, the active layer is an n-type Si layer or n-type InP layer. The source electrode 3a and the drain electrode 3b which should make ohmic contact with the active layer 2 are photolithographically formed on opposite sides of the region of the active layer 2 that is to be doubly recessed.
Then, as shown in FIG. 9(b), a resist pattern 7 is formed by photolithography. In particular, the resist film 7 is formed over the whole surface of the active layer 2. An opening 7a is formed between the source electrode 3a and the drain electrode 3b by exposure and development. Thereafter, using this resist pattern 7 as a mask, the active layer 2 is etched by an appropriate method, for example, reactive ion etching (RIE) or wet chemical etching. In this way, the first recess 6 is formed in the active layer 2 (FIG. 9(c)).
After removing the resist pattern 7, a resist pattern 8 having an opening 8a in the center of the first recess 6 is formed by photolithography in the same way as in the foregoing process (FIG. 9(d)). Using the resist pattern 8 as a mask, the active layer 2 is etched to form the second recess 5 (FIG. 9(e)).
Then, the material of the gate electrode is deposited over the whole surface of the laminate, and the gate electrode 4 is formed by the lift-off technique. In this example, the Ti layer is deposited to a thickness of 1000 angstroms, the Pt layer is deposited to a thickness of 1000 angstroms, and the Au layer is deposited to a thickness of 3000 angstroms (FIG. 10(a)). Subsequently, the resist pattern 8 is removed, forming the gate electrode 4 in the second recess 5 within the hole 20 (FIG. 10(b)).
In the above-described fabrication method, the two recesses are formed one after another. This process is complicated and requires a long time to be carried out. Furthermore, the manufacturing yield is low.
More specifically, the formation of each at the recesses 5 and 6 needs a lithography step. Therefore, and an etching step therefore it takes long to form the two recesses. In addition, it is very difficult to correctly place the second recess 5 within the first recess 6. Actually, the second recess often fails to nest in the first recess. This is one major factor providing a low manufacturing yield.
Japanese Patent Publication No. 1-286369 discloses a method of fabricating MESFETs having different threshold values on the same substrate. Specifically, semiconductor layers of dissimilar etch rates are grown on top of each other to form channel regions. The upper semiconductor layer is selectively etched, using a first mask, to expose selected portions of the lower semiconductor layer of an etch rate different from that of the upper layer. Under this condition, a second mask having openings corresponding to the selected portions of the upper semiconductor layer and to the exposed portions of the lower semiconductor layer is formed. The semiconductor layers exposed in the openings of the mask are etched in such a way that one of the two semiconductor layers remains unetched in one etching step. However, this method is unsuccessful in solving the problem of the alignment of the two masks. Also, the number of etching steps cannot be reduced.
Japanese Patent Publication No. 64-7664 discloses a method of fabricating a field-effect transistor having the doubly etched structure. In this method, a layer to be etched is selectively implanted with ions to vary the etch rate of the selected portions of the etched layer. Thus, the doubly recessed structure is formed by its self-aligning characteristic in one etching step. In this method, however, the boundary between the implanted region and the region not implanted is not sharp. Therefore, it is difficult to control the profiles of the recesses. In addition, it is impossible to form a structure having three or more recesses on different levels.
Moreover, in this method, the second recessed region has a higher etch rate than that of the first recessed region and so etching of these two regions must be started simultaneously. That is, a mask having openings corresponding to the feature of the second recessed region is needed during ion implantation. In addition, a mask having openings corresponding to the first recessed region is required during etching. A mask fabrication process using an undercutting procedure is necessitated to form the latter mask.
Japanese Patent Publication No. 1-223771 discloses a further method of fabricating the doubly recessed structure. In particular, an insulating film is formed on the channel region of a semiconductor layer having source and drain electrodes thereon. A photoresist layer having openings corresponding to the second recessed region is formed on the insulating film. Using the photoresist layer as a mask, the insulating film is anisotropically etched and then the semiconductor layer is etched to a given depth. Subsequently, the insulating film is undercut. Using this insulating film as a mask, an etching step is carried out to form the first recess. In this method, it is necessary to form only one resist mask. Nonetheless, the mask is required to be undercut in the same way as in the process described in the above-cited Japanese Patent Publication No. 64-7664. Furthermore, the process is quite complex, because plural etching techniques must be employed.